Charge pumps use a switching process to provide a DC output voltage larger than its DC input voltage. In general, a charge pump will have a capacitor coupled to switches between an input and an output. During one clock phase, the charging half cycle, the capacitor couples in parallel to the input so as to charge up to the input voltage. During a second clock phase, the transfer half cycle, the charged capacitor couples in series with the input voltage so as to provide an output voltage twice the level of the input voltage. This process is illustrated in FIGS. 1a and 1b. In FIG. 1a, the capacitor 5 is arranged in parallel with the input voltage VIN to illustrate the charging half cycle. In FIG. 1b, the charged capacitor 5 is arranged in series with the input voltage to illustrate the transfer half cycle. As seen in FIG. 1b, the positive terminal of the charged capacitor 5 will thus be 2*VIN with respect to ground.
The generic charge pump described above will transfer power only during the transfer half cycle. U.S. Pat. No. 5,436,587, the contents of which are hereby incorporated by reference, discloses a charge pump having a voltage adder stage followed by a plurality of voltage doubler stages, wherein each stage transfers power on every clock phase. Each stage includes two capacitors that cycle according to a charging half cycle and a transfer half cycle as described above. However, the two capacitors are driven in a complementary fashion such that when one is charging the other is transferring power and vice versa. In this manner, each stage may transfer power during each clock phase. The voltage adder stage may be denoted an adder because, in response to receiving a DC supply voltage (VCC) and a CLK signal of amplitude VCC, the adder stage provides a DC output voltage equal to VCC+VCC. The voltage doubler stages are arranged in series such that the Nth voltage doubler stage receives as its input voltages the output voltages produced by the (N−1)th voltage doubler stage. The voltage doubler stages may be denoted as doublers because each voltage doubler stage receives an input voltage and provides an output voltage equaling twice its input voltage. Although the voltage doubler stages provide higher output voltages than that produced by the voltage adder stage, greater voltage stress occurs across the capacitors in the voltage doubler stages as compared to those in the voltage adder stage. Specifically, the capacitors in the Nth voltage doubler stage will have to withstand a voltage stress of VCC*2(N−1), whereas the capacitors in the voltage adder stage need withstand only a voltage stress of VCC. Because the capacitors in the voltage doubler stages must withstand greater voltage stresses, these capacitors require a thicker oxide insulation layer to prevent dielectric breakdown and shorting. In general, if the maximum voltage to be sustained between the plates of a capacitor is increased by a factor of m, the separation must also be increased by this same factor.
The thicker oxide required for the capacitors used in voltage doubler stages affects the chip area required for these stages as follows. Although this discussion assumes a parallel plate topology for the capacitors used, it is equally applicable to other capacitor topologies. A parallel plate capacitor's capacitance C is proportional to the area A of the capacitor's plates divided by their separation D. In an integrated circuit process a specific oxide thickness is generally provided that is optimized to reliably sustain the power supply voltage, VCC, and is typically called the gate oxide thickness. There is often one other oxide thickness provided that can reliably sustain the output voltage of the main charge pump, and this oxide may be referred to as the high voltage gate oxide. Typically this oxide thickness is 3 to 8 times thicker than that of the gate oxide and often only one type of transistor is provided with this oxide thickness (usually nMOS). Unfortunately it is very difficult and/or costly to provide additional oxides whose thickness can be optimized for any specific multiple of VCC. To achieve the same capacitance C as D is increased, the area A of each capacitor required to sustain more than VCC must also increase by a factor of 3 to 8, and this significantly decreases the amount of chip real estate available for other uses. This factor is so significant that the capacitor area may totally eclipse the area associated with all of the control transistors.
Another type of charge pump is disclosed in U.S. application Ser. No. 10/260,115 entitled “Charge Pump with Fibonacci Number Multiplication,” filed Sep. 27, 2002, the contents of which are hereby incorporated by reference. In this type of charge pump the voltage output of a given stage is the sum of the outputs of the preceding two stages. The disclosed implementation includes one capacitor per stage, but like that shown in U.S. Pat. No. 5,436,587 referenced earlier, the capacitor must be capable of sustaining a progressively higher voltage at each stage, and thus suffers the same disadvantage of large capacitor area.
Accordingly, there is a need in the art for area-efficient charge pumps.